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The memory circuit of claim 1, wherein the memory array includes 6-transistor (6T) static random access memory (SRAM) cells, 8-transistor (8T) SRAM cells, or 10-transistor (10T) SRAM cells at intersections of the rows with the column. Sensing circuitry coupled to the column, to sense voltage on the column andĪ processor in the memory circuit to compute a multiply-accumulate (MAC) value based on the voltage sensed on the column.
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